AUTOSAR OS essentials: understand OSEK heritage and how AUTOSAR OS integrates into ECU projects.
From concepts and configuration to runtime behavior: tasks, ISRs, priorities, resources and synchronization.
Events, alarms, counters and schedule tables for time‑driven systems.
Gain practical experience with configuration labs and vendor‑neutral ARXML.
How this helps: confidently configure tasking, timing and protection in real projects.
Who it’s for: designed for individuals with embedded/automotive background learning AUTOSAR OS.
Includes debugging hooks, multicore IOC and protection features.
Curriculum
Fundamentals
- What AUTOSAR OS provides; relationship to RTE and BSW
- OSEK/VDX heritage and terminology; OS objects taxonomy
- Scalability Classes (SC1–SC4) vs. OSEK Conformance Classes (BCC/ECC) — when each matters
Tasks and ISRs
- Basic vs. Extended tasks; activation, states, priorities; preemptive vs. non-preemptive
- ISRs Category 1/2; context and nesting; stack considerations
- Hooks: StartupHook/ShutdownHook, PreTaskHook/PostTaskHook, ErrorHook
Resources, critical sections and synchronization
- Resources and internal resource; Priority Ceiling Protocol and deadlock avoidance
- Spinlocks for multicore; interrupt control and critical sections
- Trusted functions (overview)
Events, alarms and counters
- Events for Extended tasks (SetEvent/WaitEvent/ClearEvent) and state transitions
- Alarms tied to counters; relative vs. absolute; auto-start and cyclic alarms
- Counters, tick rate and time base selection
Schedule tables and time management
- Schedule tables vs. alarms; expiry points and actions (ActivateTask, SetEvent, etc.)
- Synchronizing schedule tables; next expiry, repeating and explicit synchronization
- Using schedule tables for periodic control
Protection and multicore operation
- Timing protection (budgets, overruns, protection violations)
- Memory protection (OS-Applications, MPU regions, supervisor/user modes)
- Inter-OS-Application Communication (IOC)
- Core-aware configuration and distribution of tasks
Configuration, generation and troubleshooting
- ARXML configuration overview; mapping tasks, ISRs, resources, events and schedule tables
- Code generation and integration; OS startup sequence
- Troubleshooting patterns: missed activations, priority inversions, protection violations; tracing tips
Optional modules
Optional — case studies
- Designing a timing architecture with schedule tables + alarms
- Integrating OS with RTE/BSW tasks; measuring latency and jitter
- From single-core to multicore migration (spinlocks/IOC pitfalls)
Course Day Structure
- Part 1: 09:00–10:30
- Break: 10:30–10:45
- Part 2: 10:45–12:15
- Lunch break: 12:15–13:15
- Part 3: 13:15–15:15
- Break: 15:15–15:30
- Part 4: 15:30–17:30