AUTOSAR RTE in practice: model SWCs and generate the Runtime Environment end‑to‑end.
Connect VFB concepts (ports, interfaces, runnables) with concrete ARXML configuration.
Integrate with BSW for communication, I/O and diagnostics, keeping timing in mind.
Gain practical experience through focused labs on modeling, mapping and generation.
How this helps: design clear interfaces and orchestrate execution/communication confidently.
Who it’s for: designed for individuals with embedded/automotive background moving into AUTOSAR apps.
Includes tips for performance, footprint and troubleshooting common ARXML issues.
Curriculum
AUTOSAR fundamentals
- Core concepts and architecture overview
- Application layer vs. BSW; role of RTE and VFB
- Terminology: SWC, ports, port interfaces, runnables, events
BSW concepts – essentials for application engineers
- BSW layers at a glance (EcuM, BswM, SchM, OS overview)
- Communication stack overview: Com, PduR, CanIf/EthIf, CanTp/SoAd
- Diagnostics & error handling: Dcm, Dem (high-level)
- Memory stack basics: MemIf, NvM, Fee/Ea, MemMap
Application layer modeling
- SWC types: Sender–Receiver, Client–Server, Mode management, NvData
- VFB modeling: components, compositions, connections
- Ports & port interfaces (data elements, operations, mode declarations)
- Variants and feature models (variant handling)
- Runnables & events: timing, data received, operation invoked, mode switch
- Task mapping: scheduling runnables on OS tasks; priorities and timing
RTE – interface and execution model
- How the RTE mediates Application ↔ BSW; call-outs and call-ins
- APIs overview: Rte_Read/Rte_Write, Rte_Call, Rte_Switch, Rte_IrvRead/Write
- Wait points and RTE events; reentrancy and concurrency considerations
- Operating modes for RTE; performance and footprint tips
I/O and communication integration
- I/O basics: DIO/ADC/PWM – when an SWC accesses I/O via RTE
- Communication paradigms and signal/PDU modeling in Com
- CAN and Ethernet data exchange; BSW configuration touchpoints
- End-to-end data paths (SWC ↔ RTE ↔ ComStack) – tracing and test hooks
RTE generation flow
- Authoring: ARXML structure and validation basics
- Configuration: mapping ports, connectors, events, tasks
- Generation phases and artifacts; integrating generated code into the build
- Hands-on: generate RTE and run a minimal SWC composition
- Troubleshooting: typical errors (inconsistent ARXML, missing mappings)
Optional modules
Optional – advanced topics
- SOME/IP on Ethernet (concepts) and relation to VFB/Com
- Mode management patterns and state machines
- Integration testing strategies: stubbing RTE calls, SIL/HIL basics
Course Day Structure
- Part 1: 09:00–10:30
- Break: 10:30–10:45
- Part 2: 10:45–12:15
- Lunch break: 12:15–13:15
- Part 3: 13:15–15:15
- Break: 15:15–15:30
- Part 4: 15:30–17:30